There has been significant research and development activity regarding surface strain to enhance the mobility of carriers in the inversion channel of field-effect transistors (FETs) as a method to continue improve device performance. Recently, it has been shown that the incorporation strain via internal stress on the order of 100 to 1000 MPa (1 GPa) in the surface regions of integrated circuits improves the performance of both n-channel metal-oxide-semiconductor (NMOS) transistors and p-channel metal-oxide-semiconductor (PMOS) transistors. Devices with strained silicon surface channels have demonstrated improved performance with higher drive currents and higher switching speeds.
For example, biaxial tensile strain, introduced by lattice mismatch between a fully relaxed Si1-xGex layer and a thin epitaxial Si layer below the transistors, has been shown to increase both electron and hole mobilities. However, the hole mobility improvement is known to degrade at high electric fields. For longitudinal uniaxial strains, different strain polarities, negative-compressive for PMOS and positive-tensile for NMOS, have been shown to result in mobility increases. These uniaxial strains can be obtained via a tensile silicon nitride capping layer used as a channel elongator for NMOS transistors and internal stresses exerted by a selective Si1-xGex spacer layer employed as a channel compressor in PMOS. In both the capping layer and spacer layer embodiments, the stress layer is disposed on the front of the die.
The implementation of these strains for complementary MOS (CMOS) process improvement requires significant modification of the standard CMOS process flow to incorporate the stresses, and thus results in a significant increase in cycle time and processing cost. Moreover, conventional surface strain techniques introduce the strain in front-end process steps which are before the high temperature source/drain (S/D) anneal. The S/D anneal is generally the final high temperature step (e.g. 950° C.) in a given CMOS process. Such high temperature processing after strain introduction limits the magnitude of the strain that can be achieved due to strain relaxation. As a result, current approaches are generally limited to stress of no more than about 1 GPa. In addition, once set by the process, the stress and resulting strain is not adjustable.
Instead of process-induced strain, external mechanical stress applied using a four-point bending apparatus has been disclosed to modify carrier transport as a function of bending-induced uniaxial strain. A variation of this method may be also employed to yield bending-induced biaxial strain. While such a bending apparatus may have merit for laboratory studies of strain effects on carrier transport, such an apparatus is clearly not suitable for integration into the CMOS process nor easily implemented in an IC package.